Crate cranelift_assembler_x64

A Cranelift-specific x64 assembler.

All instructions known to this assembler are listed in the inst module. The Inst enumeration contains a variant for each, allowing matching over all these instructions. All of this is parameterized by a Registers trait, allowing users of this assembler to plug in their own register types.

// Tell the assembler the type of registers we're using; we can always
// encode a HW register as a `u8` (e.g., `eax = 0`).
pub struct Regs;
impl Registers for Regs {
    type ReadGpr = u8;
    type ReadWriteGpr = u8;
    type ReadXmm = u8;
    type ReadWriteXmm = u8;
}

// Then, build one of the `AND` instructions; this one operates on an
// implicit `AL` register with an immediate. We can collect a sequence of
// instructions by converting to the `Inst` type.
let and = inst::andb_i::new(Imm8::new(0b10101010));
let seq: Vec<Inst<Regs>> = vec![and.into()];

// Now we can encode this sequence into a code buffer, checking that each
// instruction is valid in 64-bit mode.
let mut buffer = vec![];
let offsets = vec![];
for inst in seq {
    if inst.features().contains(&Feature::_64b) {
        inst.encode(&mut buffer, &offsets);
    }
}
assert_eq!(buffer, vec![0x24, 0b10101010]);

With an Inst, we can encode the instruction into a code buffer; see the example.

Modules

• inst
  Expose all known instructions as Rust structs; this is generated in build.rs.
• isle
  Expose the ISLE-related code generated in build.rs.

Macros

• isle_assembler_methods

Structs

• AmodeOffset
  A 32-bit immediate for address offsets.
• AmodeOffsetPlusKnownOffset
  An AmodeOffset immediate with an optional known offset.
• Constant
  Wrap CodeSink-specific constant keys.
• Gpr
  A general purpose x64 register (e.g., %rax).
• Imm8
  An 8-bit immediate operand.
• Imm16
  A 16-bit immediate operand.
• Imm32
  A 32-bit immediate operand.
• Label
  Wrap CodeSink-specific labels.
• NonRspGpr
  Like Gpr, but with %rsp disallowed.
• RexFlags
  A small bit field to record a REX prefix specification:
• Simm8
  A signed 8-bit immediate operand (suitable for sign extension).
• Simm16
  A signed 16-bit immediate operand (suitable for sign extension).
• Simm32
  A signed 32-bit immediate operand (suitable for sign extension).
• TrapCode
  Wrap CodeSink-specific trap codes.
• Xmm
  An x64 SSE register (e.g., %xmm0).

Enums

• Amode
  x64 memory addressing modes.
• DeferredTarget
  For RIP-relative addressing, keep track of the CodeSink-specific target.
• Extension
  Define the ways an immediate may be sign- or zero-extended.
• Feature
  A CPU feature.
• GprMem
  A general-purpose register or memory operand.
• Inst
  An assembly instruction; contains all instructions known to the assembler.
• Scale
  The scaling factor for the index register in certain Amodes.
• Size
  A single x64 register encoding can access a different number of bits.
• XmmMem
  An XMM register or memory operand.

Traits

• AsReg
  Describe how to interact with an external register type.
• CodeSink
  Describe how an instruction is emitted into a code buffer.
• KnownOffsetTable
  A table mapping KnownOffset identifiers to their i32 offset values.
• RegisterVisitor
  Describe a visitor for the register operands of an instruction.
• Registers
  A type set fixing the register types used in the assembler.

Functions

• generated_files
  List the files generated to create this assembler.

Type Aliases

• KnownOffset
  A KnownOffset is a unique identifier for a specific offset known only at emission time.